There has been much written about the use of processor models to assist in the development of software. Back in the 1970′s the early versions of Unix on a PDP11 included a simulator of the Motorola 6800 – one of the first Instruction Set Simulators made readily available. It ran very slowly and its focus was to explore the details of the instructions. Today processor models and simulators can have various usage targets.
The Instruction Set Simulators (ISS) listed on this site use the Imperas simulator infrastructure and the OVP Fast CPU Models which are all available from OVP and are written to be Instruction Accurate and are targeting the development of embedded software. Please search elsewhere for models to be used to test pipelines, cache behaviors, branch predictors and other aspects related to low level performance or power analysis of cpu architectures.
These Information pages list some of the relevant companies, organizations, and players in the ISS, CPU modeling and Virtual Platforms ecosystem.
The Information menu provides access to several pages of information:
The page information/features-of-the-imperas-instruction-set-simulator/ provides information and links about the features of the Imperas Instruction Set Simulator (ISS).
The page information/upgrading-the-imperas-iss/ provides information and links about how to add more features to the ISS and to upgrade to use some of the optional features.
The page information/downloading-an-instruction-set-simulator/ introduces how to get the ISS for the CPU you are interested in.
The links page provides links and information on the ISS, Fast CPU Models and Virtual Platform ecosystem..
Currently available Instruction Set Simulator (ISS) Families.